1. Field of the Invention
The present invention relates generally to multiport memories including a plurality of ports which can be accessed independently of each other and, more particularly, relates to structures for effectively avoiding access conflict in dual port memories having two ports.
2. Description of the Background Art
A multiprocessor system has been often used for enhancing performance of a data processing system in recent years. A multiprocessor system is a system including a plurality of CPUs (Central Processing Units). The CPUs operate asynchronously with each other. A multiport memory is used in order to carry out data transmission between the CPUS in an asynchronous manner. The multiport memory includes a plurality of ports which can be accessed independently of each other. A multiport memory having two ports is called a dual port memory.
FIG. 6 is a diagram schematically showing a structure of a multiprocessor system. In FIG. 6, a dual port memory 120 is located between a first CPU 100 and a second CPU 110. Dual port memory 120 includes an L port 120L and an R port 120R which can be accessed independently of each other. L port 120L includes a control input port CTL for receiving a control signal, a data input/output port IOL for inputting/outputting data, and an address input port ADL for receiving an address signal. Similarly, R port 120R includes a control signal input port CTR, a data input/output port IOR and an address input port ADR. The first CPU 100 is capable of input/output of data with L port 120L of dual port memory 120.
R port 120R is capable of input/output of data with the second CPU 110. L port 120L and R port 120R can operate independently of each other. Accordingly, CPUs 100 and 110 can access the dual port memory 120 and write/read data asynchronously with each other. As a result, the first CPU 100 and the second CPU 110 can transmit data therebetween while operating asynchronously with each other, using the dual port memory 120 as a buffer memory.
FIG. 7 is a diagram schematically showing the structure of the dual port memory. In FIG. 7, dual port memory 120 includes a memory cell array 211 commonly provided for R port 120R and L port 120L. Memory cell array 211, the structure of which will be described later, includes a plurality of memory cells arranged in a matrix of rows and columns.
R port 120R includes an address buffer 212 for receiving an address A0 (R) to An (R) supplied to address input port ADR and generating an internal address, a row decoder 213 for decoding an internal row address from address buffer 212 and selecting a corresponding row in memory cell array 211, a column decoder 214 for decoding an internal column address from address buffer 212 and selecting a corresponding column in memory cell array 211, and an I/O buffer (input/output circuit) 215 for transmitting data between data input/output port IOR and a memory cell selected by row decoder 213 and column decoder 214. I/O buffer 215 generates internal write data from write data DIN (R) supplied to data input/output port IOR. I/O buffer 215 also generates external read out data DOUT (R) from data on a column selected by column decoder 214.
Control on data input and output by I/O buffer 215 is performed by a control circuit (not shown). Although FIG. 7 shows as if I/O buffer 215 is connected to column decoder 214, actually, a corresponding column is selected by column decoder 214 from memory cell array 211 and the selected column is connected to an internal data bus. I/O buffer 215 is connected to the internal data bus. FIG. 7, does not show the structure of a selection gate for connecting a column selected by column decoder 214 to the internal data bus, in order to simplify the figure.
Similarly, L port 120L includes an address buffer 216 for generating an internal address from an address A0 (L) to An (L) supplied to address input port ADL, a row decoder 217 for decoding an internal row address from address buffer 216 and selecting a corresponding row in memory cell array 211, and a column decoder 218 responsive to an internal column address from address buffer 216 for selecting a corresponding column in memory cell array 211. L port 120L further includes an I/O buffer 219 for transmitting data between a memory cell in memory cell array 211 selected by row decoder 217 and column decoder 218 and an external portion (CPU) of the device. In data writing operation, I/O buffer 219 generates internal write data from external write data DI (L) supplied to data input/output port IOL and transmits the same onto a column within memory cell array 211 selected by column decoder 218. In data reading operation, I/O buffer 219 generates external read out data DOUT (L) from data on a column in memory cell array 211 selected by column decoder 218 and transmits the same to data input/output port IOL.
CPUs 110 and 100 connected to R port 120R and L port 120L can operate to perform addressing independently of each other. Dual port memory 120 shown in FIG. 7 has an L port control circuit and an R port control circuit, each of which is not explicitly shown, and each port can operate independently of each other under the control of the control circuits. Accordingly, CPU 100 and CPU 110 can operate in an asynchronous manner to carry out addressing and read out/write data from/into a corresponding memory cell.
As CPU 100 and CPU 110 operate independently of each other, there are some cases, where an address A0 (L) to An (L) supplied to L port 120L is the same as an address A0 (R) to An (R) supplied to R port 120R and the same memory cell is selected in memory cell array 211. A state in which the address A0 (L) to An (L) supplied to L port 120L is totally the same as the address A0 (R) to An (R) supplied to R port 120R is called "address conflict" or "access conflict". If such an address conflict or access conflict is caused, an unpreferable situation is brought about in a case in which either of L port 120L and R port 120R is in a data writing mode though there is no problem in a case in which both of them are in a data reading mode. A description will be made below of this situation.
FIG. 8 is a diagram showing a structure of a portion related to a memory cell of 1 bit in memory cell array 211. In FIG. 8, a memory cell MC has a memory cell structure of a flipflop type. FIG. 8 illustrates a structure of an inverter latch in which memory cell MC includes a pair of inverters in anti-parallel connection. Storage nodes Na and Nb in memory cell MC latch data complementary to each other.
Two word lines WLL and WLR and two pairs of bit lines BLL and BLR are provided for memory cell MC. A word line driving signal WLL from row decoder 217 for the L port shown in FIG. 7 is transmitted to word line WLL and a word line driving signal WLR from row decoder 213 for the R port shown in FIG. 7 is transmitted to word line WLR. Here, a signal line and a signal to be transmitted onto the signal line are represented by the same reference numeral. One row of memory cells are connected to word lines WLL and WLR.
Bit line pair BLL includes bit lines BLLa and BLLb on which data complementary to each other are transmitted. Bit line pair BLR includes bit lines BLRa and BLRb on which data complementary to each other are transmitted.
For memory cell MC, there are provided transfer gate transistors STLa and STLb responsive to a signal potential on word line WLL for connecting storage nodes Na and Nb of memory cell MC to bit lines BLLa and BLLb, respectively, and transfer gate transistors STRa and STRb responsive to a signal potential on word line WLR for connecting storage nodes Na and Nb to bit lines BLRa and BLRb, respectively.
For bit line pair BLL, there are provided column selection gates CSLa and CSLb which are turned on in response to a column select signal CDLi from column decoder 218 for the L port shown in FIG. 7, for connecting bit lines BLLa and BLLb to internal data bus lines CBLa and CBLb for the L port, respectively.
For bit line pair BLR, there are provided column selection gates CSRa and CSRb which are turned on in response to a column select signal CDRi from column decoder 214 for the R port shown in FIG. 7, for connecting bit lines BLRa and BLRb to internal data bus lines CBRa and CBRb for the R port.
One column of memory cells are connected to bit line pairs BLL and BLR. Internal data bus lines CBLa and CBLb constitute an internal data bus CBL and internal data bus lines CBRa and CBRb constitute an internal data bus CBR. Internal data bus CBL is connected to I/O buffer 219 for the L port shown in FIG. 7 and internal data bus CBR is connected to I/O buffer 215 for the R port shown in FIG. 8.
In the structure shown in FIG. 8, if word line WLL is selected, memory cell MC is connected to bit line pair BLL (bit lines BLLa and BLLb). If word line WLR is selected, memory cell MC is connected to bit line pair BLR (bit lines BLRa and BLRb). Bit line pairs BLL and BLR are connected to internal data buses CBL and CBR by column select signals CDLi and CDRi, respectively.
In a case of an address conflict or access conflict, word lines WLL and WLR are simultaneously selected and bit line pairs BLL and BLR are also selected.
If L port 120L and R port 120R are both in the data reading mode, data of memory cell MC is transmitted to common internal data buses CBL and CBR, causing no problem.
Now consider a case where L port 120L writes data into memory cell MC and R port 120R reads out data from the same memory cell MC. If data is written into memory cell MC from L port 120L, the contents stored in memory cell MC change according to the written data. Accordingly, R port 120R can not read out the contents stored in memory cell MC before the data writing, so that correct data can not be read out. That is, according to the timing relationship between the point of reading out data from R port 120R and the point of change of the contents stored in memory cell MC due to data writing from L port 120L there are cases (1) where data of changed content stored in memory cell MC is read out, (2) where data before change is read out, and (3) where the time of reading data just coincides with the time of data change (a cross point of information on the bit lines), so that data is not settled and can not be read out correctly.
Therefore, in the case of the access conflict, it is necessary to perform access arbitration, in which if at least one of the CPUs requires data writing, access by only one port is permitted and access by the other port is inhibited.
A conflict avoidance circuit 220 as shown in FIG. 7 is generally provided in order to prevent such an access conflict. Conflict avoidance circuit 220 receives an address ADL and a chip select signal *CSL supplied to the L port and an address ADR and a chip select signal *CSR supplied to the R port. Conflict avoidance circuit 220 determines which of the addresses ADL and ADR of the two ports is settled first if the address ADL from the L port and the address ADR from the R port coincide with each other. In accordance with the result of the determination, conflict avoidance circuit 220 accepts accessing to the port for which the address was settled first, making it possible to access the port while generating a busy signal BUSY indicating prohibition of accessing to the other port and inhibiting data accessing to the other port.
As a method for conflict avoidance circuit 220 to determine which port should be accessed first, there two methods of detecting the point of change of the address and of detecting the point when the chip select signal is brought to an active state. A specific structure of such a conflict avoidance circuit is described, for example, in Japanese Patent Laying-Open No. 1-303694, and Japanese Patent Laying-Open No. 62-217481.
With use of this conflict avoidance circuit 220, even if the addresses of the two ports are the same, accessing is only allowed for the port for which the address was settled first, so that no access conflict is caused and data can be processed correctly.
While the bit width of data in such a dual port memory is 8 bits in many cases, the data bit width has been increasing, such as 16 bits and 32 bits in a CPU in recent years. In such a case, it is necessary to use a plurality of dual port memories. As shown in FIG. 9, word data and byte data are included in data required by a CPU of 16 bits, even if a dual port memory of a data width of 16 bits is employed for the CPU of 16 bits. It is necessary in a dual port memory of 16 bits as well to divide the dual port memory of 16 bits into two memory blocks, i.e., a high order byte memory and a low order byte memory and to enable accessing on an 8-bit basis as the word data includes 16 bits and the byte data includes 8 bits.
If two memories or memory blocks are employed and a conflict avoidance circuit is provided for each memory or memory block in this way, access conflict can not be efficiently avoided. This problem will be discussed in the following.
FIG. 10 is a diagram showing a schematic structure of a dual port memory of 16 bits which can be accessed on an 8-bit basis. A dual port memory 300 includes a high order byte memory block (or memory chip) 310 for supplying data of high order byte and a low order byte memory block (or memory chip) 320 for inputting/outputting data of low order byte. For high order byte memory block 310, a conflict avoidance circuit 311 is provided for avoiding conflict with the high order byte data. For low order byte memory block 320, there is provided a conflict avoidance circuit 321 for avoiding an access conflict for the data of low order byte. High order byte memory block 310 inputs/outputs high order byte data DLH and DRH independently through the L port and the R port, respectively. Conflict avoidance circuit 311 determines whether or not there is a conflict of accessing to the L port and the R port for respective high order byte data, then performs a conflict avoiding operation according to the result of the determination and supplies access enabling signals (busy signals) BYLH and BYRH indicating whether or not the L port and the R port can be accessed, respectively.
Low order byte memory block 320 inputs/outputs low order byte data DLL and DRL through the L port and the R port. Access conflict avoidance circuit 321 determines whether or not there is a conflict in accessing through the L port and the R port for the low order byte data, performs an access conflict avoiding operation according to the result of the determination, and supplies access enabling signals BYLL and BYRL to the L port and the R port, respectively. In the case of the structure shown in FIG. 10, access conflict avoidance circuit 311 provided for memory block 310 and access conflict avoidance circuit 321 provided for low order byte memory block 320 perform conflict avoiding operations independently of each other. Accordingly, with this structure, if the L port and the R port are accessed on a byte basis, data can be input/output according to the conflict avoiding operations by the respective conflict avoidance circuits.
If one port is accessed on a byte basis and the other port is accessed on a word basis, since the byte data and the word data normally have different addresses with each other, no access conflict is caused and data can be input/output according to the avoiding operations of conflict avoidance circuits 311 and 321 in this case as well.
If the both ports are accessed on a word basis, however, a problem arises. Conflict avoidance circuits 311 and 321 each have independent circuit structures. In this case, the determination result by conflict avoidance circuit 311 may be different from that by conflict avoidance circuit 321 as the operation characteristics are different due to fluctuations of circuit parameters during manufacturing processes and as signal delays in signal wirings inside the circuits are different.
For example, there may be a case where conflict avoidance circuit 311 for the higher order byte data gives priority to the L port while conflict avoidance circuit 321 for the low order byte data gives priority to the R port. In this case, the CPU can not input/output data on a word basis. For such a situation, two cases can be considered as a method of accessing data by the CPU, that is, (1) in which data is input/output on the basis of a byte for which accessing is permitted and the remaining byte data is accessed again or is brought to a wait state and (2) in which accessing is repeated until access on a word basis is permitted. In either case, the processing speed of the CPU is considerably decreased.
Japanese Patent Laying-Open No. 63-29378, for example, discloses a structure in which only one access conflict avoidance circuit is operated for a plurality of memory circuits or memory blocks and access arbitration for all the memory circuits or memory blocks is carried out according to the determination result of the one access conflict avoidance circuit in order to overcome the disadvantage of the structure where access conflict avoiding operations are independently performed for the plurality of memory circuits or memory blocks.
FIG. 11 is a diagram showing an outside structure of a memory device described in the above-mentioned prior art reference, for carrying out access arbitration for a plurality of memory circuits (memory blocks) using a conflict avoidance circuit provided in one block. In FIG. 11, the memory device includes memory circuits 410 and 420. Memory circuits 410 and 420 may be formed on separate chips, or may be memory blocks formed on the same chip and capable of operating independently of each other. Memory circuits 410 and 420 have the same structures and include L ports and R ports which can be accessed independently. The both L ports of memory circuits 410 and 420 constitute an L port 440 and the both R ports of memory circuits 410 and 420 constitute an R port 430. Memory circuit 410 and memory circuit 420 can be accessed independently of each other.
The L port of memory circuit 410 includes a terminal *CSL for receiving a chip select signal .phi.USL, a terminal *CSIL for receiving a chip select signal .phi.LSL for the other memory circuit 420, a terminal CONL for supplying the result of determination of access conflict avoidance, a terminal I/OL for inputting/outputting data, and an address input terminal ADL for receiving an address L. Terminal CONL supplies to the CPU a signal CONL indicating whether or not the port can be accessed, which corresponds to a normal busy signal (BUSY signal).
Similarly, the R port of memory circuit 410 includes a terminal *CSR for receiving a chip select signal .phi.USR, a terminal *CSIR for receiving a chip select signal .phi.LSR supplied to the other memory circuit 420, a terminal CONR for supplying a signal CONR indicating the result of conflict avoidance determination, a data input/output terminal I/OR and an address input terminal ADR for receiving an address R. Memory circuit 410 further includes a control terminal MM for receiving a control signal .phi.M for enabling/disabling the access conflict avoidance circuit included therein.
The L port of memory circuit 420 includes a terminal *CSL for receiving a chip select signal .phi.LSL, a terminal CONL for receiving a signal CONL indicating the result of access conflict avoidance determination from memory circuit 410, a terminal I/OL for inputting/outputting data, and an address input terminal ADL for receiving an address L. Similarly, the R port of memory circuit 420 includes a terminal *CSR for receiving a chip select signal .phi.LSR, a terminal CONR for receiving a signal CONR indicating the result of conflict avoidance determination from memory circuit 410, a terminal I/OR for inputting/outputting data, an address input terminal ADR for receiving an address R, and a terminal MM for receiving a control signal *.phi.M for enabling/disabling an access conflict avoidance circuit included therein. The control signal *.phi.M is an inverted signal of the control signal .phi.M. In the structure shown in FIG. 11, the access conflict avoidance circuit included in memory circuit 410 is enabled and the access conflict avoidance circuit included in memory circuit 420 is disabled. Terminals *CSIL and *CSIR of memory circuit 420 are both brought into an open state. The same address L is applied to address input terminal ADL of memory circuit 410 and address input terminal ADL of memory circuit 420. The same address R is supplied to address input terminal ADR of memory circuit 410 and address input terminal ADR of memory circuit 420. In this structure, the chip select signals .phi.USL, .phi.USR, .phi.LSL and .phi.LSR select high order byte data only, low order byte data only, or the word data.
In the structure shown in FIG. 11, the access conflict avoidance circuit included in memory circuit 410 is operated to generate conflict avoidance determination result indicating signals CONL and CONR according to the signals .phi.USL, .phi.USR, .phi.LSL, and .phi.LSR and the addresses L and R supplied to terminals *CSL, *CSR, *CSIL, *CSIR, ADL and ADR.
Memory circuit 420 is enabled in response to the control signals .phi.LSL and .phi.LSR, the address L (ADL) and the address R (ADR), and writes/reads data corresponding to one port according to the conflict avoidance determination result indicating signals CONL and CONR from memory circuit 410 when an access conflict is caused. That is, in memory circuits 410 and 420, data is written/read out according to the result of avoidance determination of the access conflict avoidance circuit included in memory circuit 410.
If data is written in/read out from memory circuit 420, the chip select signals .phi.LSL and .phi.LSR attain "L" level of an active state and the chip select signals .phi.USL and .phi.USR attain "H" of an inactive state. The signals .phi.LSL and .phi.LSR are also supplied to terminals *CSIL and *CSIR of memory circuit 410. Memory circuit 410 operates the access conflict avoidance circuit included therein according to the signals supplied to terminals *CSIL and *CLIR, detects a conflict between addresses supplied to address input terminals ADL and ADR to perform the conflict avoidance determining operation, and supplies the result of the determination from terminals CONL and CONR. In memory circuit 420, data for one port is written/read out according to the conflict avoidance determination result indicating signals CONL and CONR from memory circuit 410 when a conflict is caused.
FIG. 12 is a diagram showing a structure of a portion related to access conflict avoidance operation in the memory circuit shown in FIG. 11. In FIG. 12, a conflict avoidance control portion includes an AND gate AN1 for receiving a chip select signals supplied to terminals *CSL and *CSIL, an AND gate AN6 for receiving chip select signals supplied to terminals *CSIR and *CSR, and a conflict avoidance circuit 450 for performing a determining operation in order to avoid a conflict according to the outputs of AND gates AN1 and AN6 and internal control signals .phi.L and .phi.R to supply a determination result signal and supplying a port enable signal according to the determination result.
The internal control signals .phi.L and .phi.R may be port enable signals from a memory control (not shown) provided for a memory port. The internal control signals .phi.L and .phi.R may be internal address signals. If the control signals .phi.L and .phi.R are internal control signals, i.e., port enable signals, an internal address signal is additionally supplied to conflict avoidance circuit 450. Conflict avoidance circuit 450 performs a conflict avoiding operation, depending on whether or not a conflict is caused and according to the result of the determination to supply an avoidance determination result signal and a port enable signal in accordance with the chip select signals .phi.USL, .phi.LSL, .phi.USR, and *.phi.LSR supplied to terminals *CSL, *CSIL, *CSIR, and *CSR and the addresses ADL and ADR.
The conflict avoidance control portion further includes tristate buffers T1 and T2 responsive to a control signal supplied to terminal MM for setting terminal CONL to be either an input terminal or an output terminal, a tristate buffer T3 for transmitting an avoidance determining operation result signal from conflict avoidance circuit 450 to tristate buffer T2, an AND gate AN2 which is enabled/disabled according to the control signal supplied to terminal MM, for taking a logical product of an internal control signal and an output of tristate buffer T3 or T1, an AND gate AN3 for taking a logical product of an L port enable signal from conflict avoidance circuit 450 and the control signal supplied to terminal MM, and an OR gate O1 for taking a logical sum of the outputs of AND gates AN2 and AN3. An L port enable signal .phi.LE is supplied from OR gate O1. The control signal .phi.LE may be a control signal for enabling/disabling the input/output circuit of the L port. The control signal .phi.LE may be a signal supplied to a decoder if the internal control signal .phi.L is an external address signal.
Also the R port, in the same way as for the L port, includes tristate buffers T5 and T6 responsive to a control signal supplied to control terminal MM for switching terminal CONR to an input terminal or an output terminal, a tristate buffer T4 for transmitting a conflict avoidance determination result signal from conflict avoidance circuit 450, an AND gate AN5 which is enabled/disabled according to a control signal supplied to terminal MM, for taking a logical product of an internal control signal .phi.R and an output of tristate buffer T4, an AND gate AN4 for taking a logical product of an R port enable signal from conflict avoidance circuit 450 and the control signal supplied to terminal MM, and an OR gate O2 for taking a logical sum of the outputs of AND gates AN4 and AN5. The R port enable signal .phi.RE is supplied from OR gate O2. The control signal .phi.RE may also be an internal address signal supplied to the decoder in the same way as the control signal .phi.LE or may be a control signal for enabling/disabling the input/output circuit. The operation thereof will now be described in the following.
If the control signal supplied to terminal MM is set at "H" level, tristate buffer T1 is brought to an output high impedance state, tristate buffer T2 is brought to an operating state, and terminal CONL becomes an output terminal for supplying an avoidance determination result signal CONL. Tristate buffers T3 and T4 are also brought to the operating state in which they transmit a conflict avoidance determination result signal from conflict avoidance circuit 450. Furthermore, AND gates AN2 and AN5 have their outputs fixed to "L", and AND gates AN3 and AN4 are brought to a state in which they transmit an L port enable signal and an R port enable signal from conflict avoidance circuit 450. In this state, OR gates O1 and O2 supply the outputs of AND gates AN3 and AN4 as an L port enable signal .phi.LE and an R port enable signal .phi.RE, respectively.
If a signal of "H" is supplied to terminal MM, tristate buffer T5 is enabled, tristate buffer T6 is brought to the output high impedance state and terminal CONR is set to be an output terminal.
In this state, if chip select signals .phi.USL and .phi.USR are supplied to terminals *CSL and *CSR, a memory control circuit included therein is enabled, and generates an internal control signal for enabling each port. The control signals .phi.USL and .phi.USR attain "L" when both of them are active and attain "H" when they both are inactive. Accordingly, the chip select signals .phi.USL and .phi.USR are supplied to conflict avoidance circuit 450 through AND gates AN1 and AN6. Conflict avoidance circuit 450 makes a determination for avoiding a conflict according to the output signals from AND gates AN1 and AN6, the control signals .phi.L and .phi.R, and the internal addresses ADL and ADR (not clearly shown in the figure; for the case in which the signals .phi.L and .phi.R do not include an internal address).
The determination result from conflict avoidance circuit 450 is supplied from terminal CONL through tristate buffers T3 and T2 and also supplied from terminal CONR through tristate buffers T4 and T5. The determination result signals of terminals CONL and CONR are supplied to terminals CONL and CONR of the other memory circuit 420 and an access conflict avoiding operation is carried out in the other memory 420 according to the determination result signals CONL and CONR.
AND gates AN3 and AN4 each transmit a port enable signal from conflict avoidance circuit 450. OR gates O1 and O2 supply port enable signals .phi.LE and .phi.RE.
If chip select signals .phi.LSL and .phi.LSR are supplied to terminals *CSIL and *CSIR from the other memory circuit 420, the memory control is not activated in memory circuit 410. At this time, conflict avoidance circuit 450 carries out the conflict avoiding operation according to the chip select signals from AND gates AN1 and AN6 and the internal addresses. If the internal control signals .phi.L and .phi.R are internal control signals, both of them are in a disabled state, a port enable signal is not supplied from conflict avoidance circuit 450 and the port enable signals .phi.LE and .phi.RE are in an inactive state. If the internal control signals .phi.L and .phi.R are address signals, while the signals .phi.LE and .phi.RE are generated, the memory control provided in each port is in an non-activated state, so that a selecting operation for the memory is not carried out and each port in the memory is disabled.
Conflict avoidance circuit 450 performs a conflict avoidance determining operation according to the addresses and the chip select signals (the outputs of AND gates AN1 and AN6) and supplies a signal indicating the result of the determination to terminal CONL through tristate buffers T3 and T2 and to terminal CONR through tristate buffers T4 and T5. Accordingly, if the other memory, i.e., the memory of high order byte is accessed, the ports of the memory are selectively enabled according to the avoidance determination result signals from terminals CONL and CONR.
A description will now be made of the operation in a case in which terminal MM is set at "L". This corresponds to the operation of the conflict avoidance circuit included in memory circuit 420 in FIG. 11. At this time, tristate buffers T2, T3 and T5 are brought to the output high impedance state of the disable state and tristate buffers T1 and T6 are enabled. The outputs of AND gates AN3 and AN4 are fixed to "L" and AND gates AN2 and AN5 are enabled. Accordingly, in this case, the port enable signals .phi.LE and .phi.RE correspond to the outputs of AND gates AN2 and AN5 since OR gates O1 and O2 transmit the outputs of AND gates AN2 and AN5.
If terminal ME is set at "L" level, the determination result signals CONL and CONR are supplied to AND gates AN2 and AN5 through tristate buffers T1 and T6. AND gates AN2 and AN5 pass the internal control signals .phi.L and .phi.R according to the avoidance determination result signals CONL and CONR. As a result, internal control signals .phi.LE and .phi.RE are supplied. In this case, since the chip select signal .phi.LSL has been supplied to terminal *CSL and the chip select signal .phi.LSR has been supplied to terminal *CSR in memory circuit 420 where terminal MM is set at "L", each memory control is in the operating state and internal control signals .phi.L and .phi.R are generated.
As stated above, it is designed to overcome disadvantages caused when the conflict avoidance circuits provided for the memory circuits are operated independently in a construction in which a plurality of memory circuits are arranged to be operable in parallel, by driving an access conflict avoidance circuit only in one memory circuit to control the operation of the plurality of memory circuits.
The following problem arises in a structure in which an access conflict avoidance determination is made with respect to a plurality of memory circuits using one access conflict avoidance circuit as stated above. That is, if high order byte data, for example, is accessed from the L port and low order byte data is accessed from the R port, no access conflict is caused, so that it is not necessary to perform a conflict avoidance determining operation. If a commonly provided access conflict avoidance circuit is used in this way, however, the access conflict avoidance determining operation is carried out (AND gates AN1 and AN6 make an access detection), and ports of each memory are controlled according to the determination result. Accordingly, in this case, an erroneous port control is carried out, causing the CPU to be in a wait state, so that data can not be processed at high speed.
If the byte data is accessed from one port and the word data is accessed from the other port, generally, no access conflict is generated since byte data and word data normally have different addresses with each other. In this case as well, the access conflict avoidance determining operation is performed, that is, an unnecessary determining operation is performed, so that the access time for the CPU is disadvantageously increased.
That is, in the structure of the conventional access conflict avoidance circuit, there are disadvantages that a correct access conflict avoidance can not be carried out and a useless access conflict avoiding operation is performed for some combination of address conflicts. The above-mentioned prior art article also discloses a structure in which the access conflict avoidance circuit is enabled all the time in one memory circuit, the access conflict avoiding operation for the other memory circuit is controlled if an access conflict is caused in the one memory circuit, while the access conflict avoiding operations are carried out independently if there is no access conflict caused in one memory circuit. However, also in this structure, the same problem is caused in which it is determined that an access conflict is caused in the one memory circuit when the high order byte data and the low order byte data are accessed independently in accessing data on a byte basis.